# VHDL Synchronous Clock Signal



## tech-it-^ (Aug 18, 2006)

Hello all,

I'm hoping someone knows VHDL relatively well. I am doing a lab for one of my classes and I have it all done, and want to do the extra credit. Unforutnatley I'm a little unsure on how to exactly do ONE part. 

That part relies on a synchronous clock signal. The other parts only relied on a manual clock signal, which was easier to implement. Some other things have changed in the design but those will be easy. I just need to figure out how to handle this clock signal. HERE is the link ftp://ftp.altera.com/up/pub/Laboratory_Exercises/DE2/Digital_Logic/Verilog/lab7_Verilog.pdf . and the part where I'm having issues is Part VI. 

It's only the clock part though. They want us to use a 50 MHz clock signal. When we use it though, our circuit switches way to rapidly, to where the human eye can't see it switching. I was wondering if there was a way to slow down this clock frequency (I have to use this frequency by the way). Maybe some sort of incrementer circuit that would cause a delay? But I'm unsure on how to do that.

If anyone knows how to do this, please get at me ASAP. Thank you so much!!!!!


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## tech-it-^ (Aug 18, 2006)

Figured it out lol, a while ago no worries. Thanks


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