# Asus P5b Deluxe Overclock Setup!



## George Safford (Sep 1, 2003)

I stumbled accross this arcticle and it kicks butt.

www.thetechrepository.com/showthread.php?t=41


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## George Safford (Sep 1, 2003)

The following info is cut and paste from all over the internet. I'm just posting this because I feel there is some good info. Red headers are new section Enjoy....

CPU Frequency, once chosen just use the + or - option on the numeric keypad to push the FSB up for down, the limit is shown top right of the bios screen and is 100 to 650fsb. Real limit for most boards dual channel is 540ish at this time.
DRAM frequency is where you choose what speed the ram will run at, on the P5B this is directly linked to the CPU Frequency, so as you push up the CPU fsb the Dram frequency pushes up with it...a nice touch from Asus.

I have decided to explain the DRAM ratio's further into the artice so now we move onto:

PCI Express frequency.90 to 150MHZ is selectable, selecting 120 or so can add a healthy boost to PCIE bandwidth if the cards you have can run this frequency. This option needs to be tested thoroughly to see how much the video cards can stand.110 is usually very safe, 120 is starting to push it a little.
PCI Clock...just set this to 33.33 and forget about it.
Spread Spectrum is best disabled for overclocking.
Memory Voltage 1.8 to 2.45V, only supply the dimms the voltage they need to get the overclock or speed stable. I recomend no more than 2.5V for DDR2 maximum and with this board hitting 2.45V max you should be safe. Remember to cool the ram with a fan if you can.
CPU Vcore Voltage Auto sets the voltage the CPU is hard coded to set, I always set this and view the voltage in the hardware monitor section of bios so I know my start point. Remember more volts = more heat, on air cooling with C2D try to stay at under 1.5V, 1.6V with water and phase change cooling.
FSB termination Voltage useful option when pushing the FSB frequency high on the CPU, adding a little voltage here can help stabalise things as you clock higher.
NB Vcore Remember the memory controller is on the NorthBridge, adding some voltage here can have a huge impact on how well the CPU and memory overclock. Just remember if you set the max 1.65V to keep the NB cooled by adding a fan over the heatsink.
SB Vcore useful for adding extra voltage to the PCIE bus when overclcoking video cards and trying to run them on an overclocked PCIE frequency, I would tend to use 1.7v as a max here.
ICH chipset voltage I have found no need to alter this during testing, some say it adds stability, I set auto.

The memory Remap feature is for when you are using 4GB of stsrem memory and XP, this option hardware maps the allocated ram from just over 2GB to just over 3GB with good performance, if you have only 2GB installed just leave this to disabled.

Configure DRAM timing by SPD if you leave this option to auto it will read the timing tables off the modules and apply them to the memory during normal operation, issue is we have found Asus force a few timing options of their own and only partially use what is coded into the SPD, this is why we always recomend end users set their memory timings manually. To do this force the SPD option to Disabled

Remember to initially set the default timings for your modules, usually manufacturers quote the timings in the following order...tCAS, tRCD, tRP and tRAS IE: 5-5-5-15. This just so happens to be the order of the top 4 options in the Asus P5B bios, so if you are unsure just work down the list setting what you see quoted on the dimms and you will be good to go.

Dram Write Recovery time 6 is ultra lose and good for high memory overclocks, 4 is about as tight as most dimms will go, keep this in mind as you test.

DRAM TRFC simple rule for this option. If your memory is Micron IC based you may be able to go as low as 20, everything else we have found 35 works best. Options are 20 25 30 35 and 42. obviously 42 is very lose and will allow higher overclocks.

TRRD Options 0 to 15, around 10 is where most leave this, no big effect on performance.
Rank Write to Read delay Real important timing, start at 10 some dimms may even need 12, tigher for more performance.
Read to Precharge delay again important timing, start at 10 with some dimms needing 12, tighter for more performance.
Write to precharge delay again another important sub timing, same rules..start at 10 or 12, tighter for more performance.
Static Read Control Disable for moderate to high overclocks.

Memory controller issues you need to know.

For the i965 chipset to stand a chance of hitting high FSB speeds some clever manipulation of the chipset internal timings are needed. Most know Intel release CPU's with various default FSB speeds, the usual suspects are 533, 800 and 1067. Celerons are usually fixed on the 533 bus but should be moving soon to the 800, most other P4 775 CPU's are 800 bus speed apart from the older Extreme Edition and the new C2D CPU's that are based on the 1067FSB.

The CPU has a set of pins or dots on the base called the BSEL . These pins or dots actually tell the board what FSB to apply to the CPU and tell the chipset what strap to run. The strap is actually a set of ram ratio's and a clock muliplier along with an internal latency setting. Try to think of the northbridge pretty much like a CPU...it uses a default frequency and a muliplier..and yes you can overclock it.In difference to a CPU though it also controls the memory and as such has internal latency settings that can be changed also.

Now....what you have to remember is as you push up the FSB on the CPU you also push up the FSB on the chipset. By default the chipset hits its max clock way before the CPU does...so what do you do?

The answer is manipulate the chipset into thinking it is working with a CPU that has a higher FSB default speed.
How this is done is by altering the BSEL signals the chipset uses and by setting the undocumented(at this time) 1333 strap...this means the chipset thinks it is working with a CPU that has a base FSB speed of 333 (quad pumped is 1333)

Now Asus have been quite slick with the P5B range of boards as they allow the chipset to overclock quite a bit before they slow it down by altering the strap, what this means is that once slowed down by the 1333 strap it is already in an overclocked state. The bad part is that between 360 and 399fsb the chipset is massively overclocked and really does struggle some what, the consequence of this is an "FSB hole" where it is hard to get the board stable. In reality all you have to do to avoid this "hole" is set 400fsb or higher as the strap changes here to 1333 and the board takes off again usually all the way to 500+FSB. I explain more on what exactly is happening here in more detail.

What would be nice is the 1333 strap coming in at 360FSB but with the internal latency set using the 1067 strap which is faster than the 1333 latency setting, this would allow the board to work well up towards 399FSB.from 400FSB you would relax the latency setting to the 1333 default and allow the board to clock all the way to 500+ without the non usable hole we see at this time. hopefully if Asus see this article they will tweak the bios to set more like what I have quoted...but for now the board is an awesome overclocker as it is by default but it has this 1 quirk.

Default ratio's on the P5B range of boards, I added a small table along side the available options explaining how these ratios are made available. 

Default 1067 strap has the following option available.
533,667,800 Or 1:1 (Sync with CPU FSB) 4:5 (async upclock) and 2:3 (async upclock) 

By strap manipulation Asus have managed to add 2 options from the 800 strap which are 889 and 1067. 889 is 3:5 (async uplclock) and 1067 is 1:2(async upclock)

All should work fine with the CPU at default speed, the issue is they work very differently once you start overclocking.

If you are looking to run high FSB speeds then you really do want to stick with 533 or 667 mode. 800 will push the ram speed way to high normally.
If you are at stock speed you may want to try 889 or 1067, the reason for this is that these ratios are based off the 800 strap so the chipset is already running faster than it is when using the default 1067 strap memory ratio options. The downside though is the chipset will in no way overclock as well, infact some are right on their limit trying to run the memory in 1067 ratio and will error quite bad. 889 though is quite nice and does allow for some moderate overclocking. With the chipset running overclocked and a moderate overclock on the CPU you may find you have a wicked fast system, just remember we are not talking huge FSB speeds though...using a dram ratio taken from the 800 strap you are limited to moderate CPU and memory overclocking as the chipset is already overclocked with the CPU at stock speed.

There is 1 last tweak to be aware of...Often known as TURBO mode. Turbo mode takes chipset overclocking to the max, on a board like the P5B deluxe it would only run at the CPU's default speed. Turbo mode would involve forcing the chipset to run the 533 strap with the memory in 1:1. Using memory that is capable of tight latencies at DDR533 you would see performance from the board as if it was running memory at DDR1000 or higher. This would be due to ultra tight 533 based chipset latency and the fact that the memory controller would be massively overclocked.

The only downside is Asus usually limit this mode to default CPU speed, as soon as you set 1FSB over default the option turns its self off.

At this time I have not seen Turbo mode in the P5B bios, would be nice to see it appear soon though for the non-overclockers looking for a little system performance boost 

I hope this small guide has been helpful, more guides are on the way as time allows, and board manufacturers send me boards (shamelss begging!!)

Parameter Description
tAL Added Latency to column accesses, used in DDRx SDRAM devices for Posted CAS commands.
tBURST
Data burst duration. The time period that data burst occupies on the data bus.
Typically 4 or 8 beats of data. In DDR SDRAM, 4 beats of data occupies 2 full clock cycles
tCAS
Column Access Strobe latency. Time interval between column access command and the start of data return by
DRAM device(s). Also known as tCL.
tCMD
Command transport duration. Time period that a command occupies on the command bus as it is transported from
the DRAM controller to the DRAM devices
tCWD
Column Write Delay. Time interval between issuance of column-write command and placement of data on data bus
by the DRAM controller.
tFAW
Four (row) bank Activation Window. A rolling time frame in which a maximum of four bank activation can be
engaged. Limits peak current profile in DDR2 and DDR3 devices with more than 4 banks.
tINT-BURST
Internal burst duration. The internal burst length of the DRAM device. Multiple internal bursts are often used to
form one longer continuous burst for column read commands. tint-burst is 2 for DDR, 4 for DDR2.
tRAS
Row Access Strobe. Time interval between row access command and data restoration in DRAM array. DRAM
bank cannot be precharged until at least tRAS time after the previous bank activation.
tRC Row Cycle. Time interval between accesses to different rows in a bank. tRC = tRAS + tRP
tRCD Row to Column command Delay. Time interval between row access and data ready at sense amplifiers.
tRFC Refresh Cycle Time. Time interval between Refresh and Activation command
tRP Row Precharge. Time interval that it takes for a DRAM array to be precharged for another row access.
tRRD
Row activation to Row activation Delay. Minimum time interval between two row activation commands to same
DRAM device. Limits peak current profile.
tRTP Read to Precharge. Time interval between a read and a precharge command. Can be approximated by tCAS - tCMD
tRTRS
Rank to rank switching time. Used in DDR and DDR2 SDRAM memory systems. Not used in SDRAM or Direct
RDRAM memory systems. 1 full cycle in DDR SDRAM
tWR
Write Recovery time. Minimum time interval between end of write data burst and the start of a precharge
command. Allows sense amplifiers to restore data to cells
tWTR
Write To Read delay time. Minimum time interval between end of write data burst and the start of a column-read
command. Allows I/O gating to overdrive sense amplifiers before read command starts
Table 1:

// DDR2 800 Mbps memory system
Fig. 4: DRAM Configuration File for DDR2 SDRAM Memory System with 512 Mbit Devices
// Composed of 512 Mbit chips. 2 ranks, each rank has 8 2 Gbit (x8) chips.
// This is a 64 bit wide interface.
// Total is 1 GB
// Bandwidth is 6.4 GB/s
// The parameters contained in this file are from Micron datasheet for MT47H64M8 -25E
//
type ddr2 // ddr2
datarate 800
clock_granularity 2 // 2 half cycles per cycle (timing listed in half cycles)
channel_count 1 // Logical channel
channel_width 8 // Byte width
PA_mapping_policyclose_page_baseline // Comments are allowed here
row_buffer_policy close_page
rank_count 2
bank_count4 // 4 banks per chip. larger chips have 8 banks.
row_count 16384 // 14 bits row address space
col_count 1024 // 10 bits col address space
t_burst 8 // burst length of 4 or 8
t_cas 10 // 5 * 2
t_faw 30 // 22.5 ns
t_ras 36 // 30 ns
t_rc 46 // 45 ns
t_rcd 10 // 12.5 ns
t_rfc 102 // takes 127 ns to do one refresh
t_rrd 6 // 7.5 ns
t_rp 10 // 12.5 ns
t_rtp 6 // 3 * 2
t_rtrs 2 // 1 * 2
t_wr 12 // 10 ns
t_wtr 6 //
posted_cas TRUE // posted CAS
t_al 10 // 4 * 2
auto_refresh FALSE // Enable auto refresh
auto_refresh_policy refresh_one_chan_all_rank_all_bank
refresh_time 64000 // 64 ms refresh time

This timings should work:
DRAM Cas latency:4
DRAM RAS to CAS:4
DRAM RAS Precharge:4
DRAM RAS activate to precharge:12
DRAM Write recovery time:4
DRAM TRFC:30
DRAM TRRD:10
Rank write to read delay:10
Read to precharge delay:10
Write to precharge delay:10

Well, that are the most "normal settings" If it's stable, you can set the four numbers of "10" into 9. If that is stable, go to eight, that's not the best way, the best way is to set them one by one as low as possible, but that's gonna take a lot of time. Look it's so that every stick of RAM react different on the same timings. You also can try to set the TRFC to 25. 

But again: It didn't makes a lot of performance with the Core 2 Duo series.

DRAM Cas: 4, DRAM Ras: 4, DRAM Ras Precharge: 4, DRAM Ras activate to Prech: 12, DRAM Write Recovery: 5, TRFC: 35, TRRD: 10, Rank Write to read delay: 10, Read to precharge delay: 10, Write to precharge delay: 10
I then set the CPU freq to 225, chose DDR2-900 for the DRAM freq, 2.05 volts for memory voltage, 1.55 volts for NB, 1.30 volts for FSB term.

Method, system and memory controller utilizing adjustable read data delay settings Document Type and Number:
United States Patent 20060129776 
Kind Code:
A1 
Link to this page:
http://www.freepatentsonline.com/20060129776.html 
Abstract:
A method, system and memory controller that uses adjustable read data delay settings. The memory controller includes control transmit circuitry, data reception circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data reception circuitry receives data signals from the memory devices via respective data signal paths. The timing circuitry delays reception of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices. 

Byte 0
Number of Serial PD Bytes written during module production
This field describes the total number of bytes used by the module manufacturer for the SPD data and any (optional) 
specific supplier information. The byte count includes the fields for all required and optional data. 
For most manufacturers, they do not insert optional data and the resulting data (in hex) would normally be:
128Byte: 80h 256Byte: FFh 

Byte 1
Total number of Bytes in Serial PD device
This field describes the total size of the serial memory used to hold the Serial Presence Detect data, 
device used is usually 128 Bytes or 256 Bytes with 256 Bytes as the most common.

256 Byte (24C02)
(34C02) with Software Write Protect function
(34C02B)with Reversible Software Write Protect function : 08h 

128 Byte (24C01): 07h 

Byte 2
Fundamental Memory Type 
This refers to the DRAM type. In this case, we are only dealing with DDR2 SDRAM.
DDR2 SDRAM: 08h 

Byte 3 
Number of Row Addresses on this assembly
This relates to the DRAM size as well as the Refresh scheme of the DRAM. 
The best way to discover this is to use the AutoID function of the CST DIMM tester. 
You would first run the AutoID on the tester. 
You then use the [Edit] [AdrDat] function to display the Row and Column Address counts.
15: 0Fh 14: 0Eh 13: 0Dh 12: 0Ch 

Byte 4 
Number of Column Addresses on this assembly
This relates to the DRAM size as well as the Refresh scheme of the DRAM. 
The best way to discover this is to use the AutoID function of the CST DIMM tester. 
You would first run the AutoID on the tester. You then use the [Edit] [AdrDat] function 
to display the Row and Column Address counts. 13: 0Dh 12: 0Ch 11: 0Bh 10: 0Ah 09: 09h

Byte 5
Module Attributes - Number of Physical Banks on DIMM, Package and Height
This is a multi-purpose field that involves calculations and bit combination. 
A Flash program combine them together and give you an automatic result after 
you have selected the different attributes.



Byte 6
Module Data Width of this assembly
This refers to the number of data bit width on the module. For a standard 8 byte DIMM, 64 bits 
would be most common while an 8 byte ECC module would have 72 bits. Some special module might 
even have up to 144 bits. In any case, a CST tester Auto ID function would tell you this number 
in plain English.
32 bit: 20h 64 bit: 40h 72 bit: 48h 144 bit: 90h

Byte 7
Reserved
Not available: 00h 

Byte 8
Voltage Interface Level of this assembly
This refers to the power supply voltage Vdd of the DIMM. Standard DDR2 SDRAM module would be SSTL 1.8V
1.8V DDR2: 05h Recommended Default

Byte 9
SDRAM Device Cycle time 
This commonly referred to the clock frequency of the DIMM. Running at its specified CL latency. 

5.0 ns (400Mhz): 50h 3.75 ns (533Mhz): 3Dh 3.0 ns (667Mhz): 30h
2.5 ns (800Mhz): 25h

Byte 10
SDRAM Device Access from Clock (tAC)
This byte defines the maximum clock to data out time for the SDRAM module. You can normally 
read off the tAC specification on the Timing Parameter table.
+/-0.6 ns: 60h
+/-0.5 ns: 50h
+/-0.45 ns: 45h
+/-0.40 ns: 40h

Byte 11
DIMM Configuration Type
This is to identify the DIMM as ECC, Parity, or Non-parity. Normally non-parity is related to 
64 bit module, Parity and ECC are related to 72 bit or higher memory bit width on the module.
NonECC: 00h 
ECC: 02h
Address/Command Parity with ECC: 06h

Byte 12
Refresh Rate
This byte describes the module's refresh rate and if it is self-refreshing or non-self refreshing. 
Today, most standard modules would be capable of self-refreshing. The refresh time is easily read 
from the DRAM manufacturer data sheet. Refresh time can be listed in two different ways.
1. In Refresh Interval Time. For example: 15.6usec. or 7.8usec.
2. In milli-seconds per x Refresh Cycles. For example: 62.4ms in 8K refresh 
This can be converted back into refresh interval time with the equation: 
Refresh Interval = Total Refresh Period/number of refresh cycles.
15.6 us Self-refresh (4K): 80h 7.8 us Self-refresh (8K): 82h 
15.6 us non Self-refresh : 00h 7.8 us non Self-refresh : 02h

Byte 13
Primary SDRAM Width
This refers to the bit width of the primary data SDRAM.
For a standard DIMM module. 4 bits: 04h 8 bits: 08h 16 bits: 10h

Byte 14
Error Checking SDRAM Width
This refers to the bit width of the error checking DRAM. For a standard module, 
it is either no ECC bit, or 8 bits on a regular 8 byte module. It can also be 16 bits on 
a 144 bit (16 byte) module.
No-ECC: 00h 8bits: 08h 16bits: 10h

Byte 15
Reserved
Not available: 00h

Byte 16
Burst Lengths Supported
This is indicates the burst length supported. In DDR2, standard DRAM are all 4, 8 burst supported.
4, 8 Burst length supported: 0Ch 

Byte 17
Number of Banks on SDRAM Device
This is referring to the internal bank on the DRAM chip. All modern DDR2 chips under 1Gbit have 
4 internal banks. For chips at 1Gbit or above, they have 8 internal banks.
4 Internal Banks: 04h 8 Internal Banks (for 1Gb or 2Gb chips only): 08h

Byte 18
CAS Latency (CL)
This refers to the all the different Cas Latency supported by your chip. This can vary with the 
frequency you operate your DIMM. This number can be read off your DRAM data sheet.
CL=3 and 4 supported: 18h
CL=4 and 5 supported: 30h
CL=5 and 6 supported: 60h
CL=5 supported: 20h
CL=6 supported: 40h

Byte 19
DIMM Mechanical Characteristics
This defines the module thickness where the maximum thickness includes all assembly parts: devices, 
heat spreaders, or other mechanical components. This information together with the DIMM type, allows 
the system to adjust for thermal operation specifications.

Byte 20
DIMM type information
This byte identifies the DDR2 SDRAM memory module type. 
Each module type specified in this Byte 20 defines a unique index for module thickness specified in Byte 19, 
which may be used in conjunction with thermal specifications in Bytes 21 and 47-61 to adjust system operation 
conditions based on installed modules.
Undefined 00h
Regular Registered DIMM: 01h
Regular Unbuffered DIMM: 02h
SO-DIMM: 04h
Micro-DIMM: 08h
Mini-Registered DIMM: 10h
Mini-Unbuffered DIMM: 20h

Byte 21
SDRAM Module Attributes
This byte involves 4 main items. Bit 0-1 signifies the number of registers on the DIMM. Bit 2-3 signifies 
the number of PLL’s on the DIMM. Bit 4 indicates if any on board FET switch is enabled. Bit 6 indicates 
if an analysis probe is installed. In most cases, Bit 4 and Bit 6 are not used. 
The resulting hex code is calculated as follows:

0 PLL chip and 1 Register chip 00h
0 PLL chip and 2 Register chip 01h
1 PLL chip and 1 Register chip 04h
1 PLL chip and 2 Register chip 05h
2 PLL chip and 1 Register chip 08h
2 PLL chip and 2 Register chip 09h

Byte 22
SDRAM Device Attributes –General
This byte is a multi-purpose byte. It includes PASR (Partial Array Self Refresh) , 50 ohm ODT enable and 
also support of Weak Driver. The resultant hex code is calculated based on the selection you made.

Supports PASR Supports 50 ohm Supports weak driver HEX

No No No 00h
No No Yes 01h
No Yes No 02h
No Yes Yes 03h
Yes No No 04h
Yes No Yes 05h
Yes Yes No 06h
Yes Yes Yes 07h

Byte 23
SDRAM Min Clock Cycle at CLX-1
This is referred to the speed (or frequency) the DRAM can run at when the Cas Latency 
is reduced by 1 clock. This data can be looked up from the datasheet of the DRAM. 
This is usually listed at the first page of the data sheet where it mentioned highest 
frequency it can run at a certain Cas latency setting. 
De-rated latency 
3.0ns (667 Mhz): 30h 
3.75 ns (533Mhz) : 3Dh 
5.0 ns (400Mhz) 50h 
Undefined: 00h

Byte 24
Max Data Access Time(tAC) at CLX-1
This is referred to DQ output access time from CK/CK* at when the Cas Latency is reduced by 1 clock. 
This data can be looked up from the datasheet of the DRAM. This is usually listed as tAC on the data 
sheet where it mention maximum frequency it can run at a certain CAS latency setting.
+/-0.45ns: 45h +/-0.5 ns: 50h +/-0.6 ns: 60h Undefined: 00h

Byte 25
SDRAM Min Clock Cycle at CLX-2
This is referred to the speed the DRAM can run at when the Cas Latency is forced to reduce by two notches. 
This data can be looked up from the datasheet of the DRAM. This is usually listed at the first page of the 
data sheet where it mentioned the frequency it can run at a certain Cas latency setting. 
3.75 ns (533Mhz): 3Dh 5.0 ns (400Mhz): 50h Undefined: 00h

Byte 26
Max Data Access Time(tAC)CLX-2
This is referred to DQ output access time from CK/CK* at when the Cas Latency is reduced by 2 clock. 
This data can be looked up from the datasheet of the DRAM. This is usually listed as tAC on the data 
sheet where it mention maximum frequency it can run at a certain CAS latency setting.
+/-0.45ns: 45h +/-0.5 ns: 50h +/-0.6 ns: 60h

Byte 27 
Minimum Row Pre-charge Time (tRP)
This is tRP min read off the DRAM data sheet. 
15 ns: 3Ch

Byte 28
Minimum Row to Row Access Delay (tRRD)
This is the tRRD min time read off the DRAM data sheet. 
(x4,x8) 7.5ns: lEh (x16) 10 ns: 28h

Byte 29
Minimum Ras to Cas Delay (tRCD)
This is the tRCD min time read off the DRAM data sheet 
15 ns: 3Ch

Byte 30
Minimum Active to Pre-charge Time (tRAS)
This is the tRAS min time read of the DRAM data sheet.
40 ns: 28h (For DDR2 533/400Mhz)
39 ns 27h (For DDR2 667 Mhz)

Byte 31
Module Bank Density
This refers to the Mega-Byte in each physical bank (per rank) on the DIMM. 
For example: if a 256MB module has two physical banks, then each physical bank 
should have 128MB.
128MB: 20h 256MB: 40h 512MB: 80h
1G: 01h 2G: 02h 4G: 04h

Byte 32
Address and Command Input Setup Time Before Clock (tIS)
This refers to the time of the address and command lines have to occur before the 
next clock edge. It is labeled as tIS min in the case of DDR2.
DDR2 (tIS) 0.2ns: 20h 0.25 ns: 25h 0.30 ns: 30h 0.35 ns: 35h

Byte 33
Address and Command Input Hold Time After Clock (tIH)
This refers to the period of time the address and command lines have to hold after 
the last clock edge has appeared. It is labeled as tIH min in the case of DDR2.
0.275 ns: 27h 0.325ns: 32h 0.375 ns: 37h 0.475 ns: 47h

Byte 34
SDRAM Device Data/Data Mask Input setup Time Before Data Strobe (tDS)
This refers to the time of the Data and Data Mask lines have to occur before the 
next clock edge. It is labeled as tDS min in the case of DDR2.
DDR2(tDS) 0.05ns: 05h 0.10 ns: 10h 0.15 ns: 15h

Byte 35
Address and Command Input Hold Time After Clock (tDH)
This refers to the period of time the Data and Data Mask lines have to hold after 
the last clock edge has appeared. It is labeled as tDH min in the case of DDR2.
DDR2(tDH)0.175ns: 17h 0.225 ns: 22h 0.275 ns: 27h

Byte 36
Write recovery time (tWR)
This byte describes the write recovery time(tWR)min 
15.0 ns: 3Ch

Byte 37
Internal write to read command delay (tWTR)
This byte describes the internal write to read command delay (tWTR)min 
7.5 ns: 1Eh 10.0 ns: 28h

Byte 38
Internal read to pre-charge command delay (tRTP)
This byte describes internal read to precharge command delay 
(tRTP) 7.5 ns: 1Eh

Byte 39
Memory Analysis Probe Characteristics
This byte describes various functional and parametric characteristics of the memory 
analysis probe connected to this DIMM slot. These characteristics may be consulted 
by the BIOS to determine proper bus drive strength to account for additional bus 
loading of the probe. It also describes functional characteristics of the probe that 
may be used to configure the memory controller to drive proper diagnostic signals to 
the probe, such as via the TEST,NC pin
Not available: 00h Default value if probe is not described

Byte 40
Extension of Byte 41 tRC and Byte 42 tRFC
This byte serves as an extension when Byte 41 or Byte 42 has run out of space to 
accommodate the bigger value
When tRFC (byte 42) is 127.5ns, byte 40 is: 06h
When tRFC (byte 42) is 327.5ns, byte 40 is: 07h
When tRC (byte 41) is 63.75ns, byte 40 is: 50h
When tRC (byte 41) is 65ns, byte 40 is: 00h

Byte 41
Minimum Active to Active Auto Refresh Time (tRCmin)
53ns: 35h 54ns: 36h 55 ns: 37h 60 ns: 3Ch
63.75ns: 8Eh 65ns: 41h

Byte 42
Minimum Auto Refresh to Active Auto Refresh Time (tRFC)
This byte identifies the minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC).
(256Mb)75 ns: 4Bh (512Mb)105 ns: 69h
(1Gb) 127.5ns: 7Fh (2Gb) 195ns: C3h
(4Gb) 327.5ns: 47h

Byte 43
Maximum Device Cycle time (tCKmax)
8 ns: 80h

Byte 44
Maximum Skew Between DQS and DQ (tDQSQ)
Maximum DQS tolerance.
0.24 ns: 18h 0.30 ns: 1Eh 0.35 ns: 23h

Byte 45
Maximum Read DataHold Skew Factor (tQHS)
Maximum DOS and DO window tolerance. 
0.34 ns: 22h 0.40 ns: 28h 0.45 ns: 2Dh

Byte 46
PLL Relock Time
This refers to the lock time on the PLL IC used in the registered module. 
You can read this off the PLL device datasheet.
Undefined: 00h 8us: 08h 10us: 0Ah 
12us: 0Ch 15 us: 0Fh

Byte 47 to Byte 61
These bytes describe the thermal characteristic of the memory chips and the logic 
chips used on the module. These are complex thermal data used in calculating the 
thermal throttling of the microprocessor speed under overstress conditions. In most systems, 
these data are ignored (or not available).

Byte 47
Tcasemax
Bits 7:4: Tcasemax Delta, the baseline maximum case temperature is 85 OC. Bits 3:0: DT4R4W Delta.
Not available: 00h

Byte 48
Psi T-A DRAM
Thermal resistance of DRAM device package from top (case) to ambient (Psi T-A DRAM)
Not available: 00h

Byte 49
DTO/Tcase Mode Bits
Bits 7:2:Case temperature rises from ambient due to IDDO/activate-pre- charge operation minus 2.8 OC 
offset temperature. Bit 1: Double Refresh mode bit. BitO High Temperature self-refresh rate support 
indication
Not available: 00h

Byte 50
DT2N/DT2Q
Case temperature rises from ambient due to IDD2N/precharge standby operation for UDIMM and due to 
IDD20/precharge quiet standby operation for RDIMM.
Not available: 00h

Byte 51
DT2P
Case temperature rises from ambient due to IDD2N/precharge standby operation for UDIMM and due to 
IDD20/precharge quiet standby operation for RDIMM.
Not available: 00h

Byte 52 
DT3N
Case temperature rises from ambient due to IDD2P/precharge power-down operation
Not available: 00h

Byte 53
DT3Pfas
Case temperature rises from ambient due to IDD3P Fast PDN Exit/active power-down with Fast PDN 
Exit operation
Not available: 00h

Byte 54
DT3Pslow
Case temperature rises from ambient due to IDD3P Slow PDN Exit/active power-down with Slow PDN 
Exit operation
Not available: 00h

Byte 55
DT4R/Mode Bit
Bits 7:1: Case temperature rises from ambient due to IDD4R/page open burst read operation. 
Bit 0: Mode bit to specify if DT4W is greater or less than DT4R
Not available: 00h

Byte 56
DT56
Bits 7:1: Case temperature rises from ambient due to IDD4R/page open burst read operation. 
Bit 0: Mode bit to specify if DT4W is greater or less than DT4R
Not available: 00h

Byte 57
DT7
Case temperature rise from ambient due to IDD7/bank interleave read mode operation
Not available: 00h

Byte 58
Psi T-A PLL
Thermal resistance of PLL device package from top (case) to ambient (Psi T-A PLL)
Not available: 00h

Byte 59
Psi T-A Register
Thermal resistance of register device package from top (case) to ambient (Psi T-A Register)
Mot available: 00h

Byte 60
DT PLL Active
Case temperature rises from ambient due to PLLin active mode atVCC = 1.9 V the PLL loading is the DIMM loading
Not available: 00h

Byte 61
DT Register Active/Mode Bit
Bits 7:1: Case temperature rises from ambient due to register in active mode at VCC = 1.9 V, 
the register loading is the RDIMM loading. Bit 0: mode bit to specify register data output toggle rate 50% or 100%
Not available: 00h

Byte 62
SPD Data Revision Code
Revision 1.0: 10h Revision 1.1: 11 h Revision 1.2: 12h

Byte 63
Checksum for Byte 0 to 62
Checksum is calculated and placed into this byte. All CST testers have automatic checksum calculation for this byte. 
All you have to do is to fill in and audit byte 0-62, the tester will automatically fill in byte 63 for you 
through the auto-checksum calculation.

Byte 64-71
Manufacturer’s JEDEC ID Code
This is a code obtained through manufacturer’s registration with JEDEC ( the standard setting committee). 
A small fee is charged by JEDEC to support and maintain this record. Please contact JEDEC office. 
Byte 64 is the most significant byte. If the ID is not larger then one byte (in hex), byte 65-71 should be 
filled with 00h.

Byte 72
Module manufacturing Location
Optional manufacturer assigned code.

Byte 73-90
Module Part Number
Optional manufacturer assigned part number.
The manufacturer’s part number is written in ASCII format within these bytes. Byte 73 is the most 
significant digit in ASCII while byte 90 is the least significant digit in ASCII. Unused digits are 
coded as ASCII blanks (20h).

Byte 91-92
Module Revision Code
Optional manufacturer assigned code.

Byte 93-94
Module Manufacturing Date
Byte 93 is the year: 2005 69h 2006 6Ah 2007 6Bh
Byte 94 is the week of the year: wk1-wk15 01h – 0Fh
wk16-wk31 10h – 1Fh
wk32-wk47 20h – 2Fh
wk48-wk52 30h – 34h

Byte 95-98
Module Serial Number
Optional manufacturer assigned number.
On the serial number setting, JEDEC has no specification on the data format nor dictates 
the location of Most Significant Bit. Therefore, it’s up to individual manufacturer to 
assign his numbering system. All CST testers and EZ-SPD programmers have the option for 
user to select either byte 95 or byte 98 as the MSB (most significant bit). The testers 
assume the use of ASCII format; which is the most commonly used. The CST testers also have 
the function to automatically increment the serial number on each module tested. 

Byte 99-127
Manufacturer’s Specific Data
Optional manufacturer assigned data.

Byte 128-255
Open for Customer Use
Optional for any information codes.

Final Note:

Everything in the above article and more are now implemented into the CST EZ-SPD DDR2 
Programmer software. The new features are:

1. Pop up window of explanation on each Byte.
2. Clickable selection right from the illustration window.
3. Auto checksum on byte 62.
4. Text input on "manufacturer code" and "serial number". User define MSB/LSB format.
5. Auto JEDEC week and year coding from PC clock.
6. Software write protect function.

.....just to name a few.

For further information, please view : www.simmtester.com 

By: DocMemory
Copyright © 2006 CST, Inc. All Rights Reserved 
1. Row activation 
Before any operation with data stored in some bank of an SDRAM chip (READ or WRITE), it's necessary to activate a corresponding row in this bank. For this purpose, the ACTIVATE command with a bank number (BA0-BA1 rows for a 4-banked chip) and row address (A0-A12 address lines, their real number depending on the number of rows in a bank; it's 213 = 8192 in this case of a 512-Mbit SDRAM chip) is given to the chip.
Activated row remains open (available) for subsequent access operations until the PRECHARGE command, which actually closes this row. Minimum period of row activity — from its activation to precharge is determined by Row Active Time (tRAS).
It's impossible to reactivate another row in the same bank, while the previous row in this bank is open (as SenseAmp, containing a data buffer the size of a single bank row, described in the section SDRAM chips: physical organization and operation principles, is shared by all rows in this bank of an SDRAM chip). Thus, a minimum period of time between activation of two different rows in the same bank is determined by Row Cycle Time (tRC).
At the same time, having activated a row in a given bank, SDRAM chip can easily activate another row in the other bank (that's the above-mentioned advantage of multibanked SDRAM) at the next cycle of the memory bus. Nevertheless, in actual fact, SDRAM manufacturers usually deliberately introduce an additional delay, called Row-to-Row Delay (tRRD). Reasons for introducing this delay have nothing to do with operation of memory chips as such. They are purely electrical — row activation consumes quite a lot of electric power, so frequent execution of this command may lead to undesirable excessive electric loads. 
2. Read/write data 
The next time parameter of memory operation appears because row activation itself requires some time. In this respect, subsequent (after ACTIVATE) READ or WRITE commands cannot be given at the next cycle of a memory bus. It can be done only after a certain interval, called RAS#-to-CAS# Delay (tRCD).
So, after an interval of tRCD, the READ command with a bank number (ACTIVATED) and a column address is given to a memory chip. SDRAM devices are intended for reading and writing data in Burst mode. It means that giving just a single READ (WRITE) command will result in reading/writing several elements, or words, in succession from/to storage cells (capacity of each word equals the width of the external data bus in a memory chip — for example, 8 bit). The number of data elements, read by a single READ command or written by a single WRITE command, is called Burst Length and usually amounts to 2, 4, or 8 elements (except for an exotic case of Full-Page Burst, when a special BURST TERMINATE command should be used to interrupt a super-long burst). Note that DDR and DDR2 memory chips cannot have Burst Length less than 2 and 4 elements correspondingly — the reason will be analyzed below in connection with differences between SDR/DDR/DDR2 SDRAM devices.
Let's get back to reading data. There exist two types of the read command. The first one is a usual READ command, the second is called Read with Auto-Precharge, (RD+AP). The latter has a peculiarity - after a burst data transfer along the data bus is completed, PRECHARGE command will be given automatically, while in the first case the selected row will remain open for further operations.
After the READ command, the first portion of data does not become available immediately, but after a delay of several memory bus cycles, when data read from SenseAmp are synchronized and transferred to the external pins of the chip. The delay between the read command and availability of data on the bus is the most important parameter, which is called CAS# Latency (tCL). The next chunks of data (in compliance with burst length) become available without any additional latencies at each next memory bus cycle (one element per cycle for SDR devices, two elements per cycle in case of DDR/DDR2 devices).
Data write operations are performed in the same way. There exist two write command types just as well — simple data write (WRITE) and Write with Auto-Precharge (WR+AP). In the same way, in case of the WRITE/WR+AP command, a bank number and a column address are fed to a memory chip. And finally, data are also written in bursts. Here are the differences between write and read operations. Firstly, the first chunk of data to be written must be fed on the data bus simultaneously with WRITE/WR+AP command, bank number, and column address sent on the address bus. The next chunks, their number determined by burst length, are sent at each next memory bus cycle. Secondly, Write Recovery Time (tWR) becomes of primary importance here, instead of CAS# latency (tCL). This value determines a minimal interval between receiving the last chunk of data to be written and readiness of a row to be closed by the PRECHARGE command. But if it's necessary to read the data from the same open row instead of closing it, another latency becomes important - Write-to-Read Delay (tWTR).
3. Row precharge 
The cycle of reading/writing data from/into memory rows, which in the general case can be called a row access cycle, ends in closing the open row using the PRECHARGE command (which can be done automatically, as part of RD+AP or WR+AP). Subsequent access to this memory bank does not become possible immediately, but after some interval, called Row Precharge Time (tRP). That's when the precharge operation is carried out - when data elements corresponding to all columns of a given row with SenseAmp return to memory row cells.
Correlations between timings 
In conclusion of this section about memory access latencies, let's review the main correlations between the most important timing parameters by giving an example of simple data read operations. As we have already written above, in the general case - burst read (2, 4, or 8 elements) - the following operations should be executed:
1) ACTIVATE a row in a memory bank 
2) Give the READ command 
3) Read the data on the external data bus of a memory chip 
4) Close the row with the PRECHARGE command (it can be done automatically, if RD+AP is used at the second step).
Time between the first and the second operation is called RAS# to CAS# delay (tRCD), between the second and the third — CAS# latency (tCL). Time between the third and the fourth operations depends on a burst length. Strictly speaking, it equals the burst length (2, 4, or 8) in memory bus cycles divided by a number of data elements, transferred on the external bus per cycle — 1 for SDR devices, 2 for DDR devices. And finally, time between the fourth operation and the next repetition of the first operation in a cycle is called Row Precharge Time (tRP).
At the same time, we have already seen above that the minimum row active time tRAS is actually the interval between the first and the fourth operations. Hence follows the first important correlation: 
tRAS > tRCD + tCL, 
minimum tRAS must be greater than the sum of tRCD and tCL by the duration of the third operation, determined by burst length. Let's consider the following example: DDR memory with tCL = 2 and tRCD = 2 (typical of high-speed DDR memory modules). In case of the minimum burst length of 2 (DDR standard), minimum 4 memory bus cycles are necessary for tRCD and tCL plus one bus cycle to read one data packet. Thus, in this case tRAS equals 5. Transferring longer packets consisting of four elements (BL = 4) increases this value to 6.
The second important correlation between timings follows from the fact that a full cycle of burst reading — from Stage 1 to its repetition is actually called Row Cycle Time, tRC. As the first three stages cannot take up less time than tRAS and the last stage takes up no less time than tRP, we get the following:
tRC = tRAS + tRP.
Note that some memory controllers (for example, integrated memory controller in AMD64 processors) allow to set tRAS and tRC independently, which may theoretically result in violation of the above equation. Nevertheless, this inequation is not important — it will just mean that tRAS or tRC will be automatically adjusted (upward) to comply with this equation.
Command interface delays 
A special group of timings, which have nothing to do with SDRAM data access, is the so called command interface delays, or their inverse characteristic — command rate. These delays have to do with low operation level of the memory system — not individual chips, but physical banks composed by them. When a memory system initializes, each physical bank gets a die number (chip select), which identifies it in each subsequent request (as all banks share the same command/address and data buses). The more physical banks, the longer delays in signal propagation (as a direct offshoot of the signal path length), encode/decode, and addressing/control logic.
That's how delays in command interface appear. They are mostly known for AMD Athlon 64 platforms with integrated memory controllers supporting DDR SDRAM. Of course, it does not mean that command interface delays are characteristic of this platform only — it's just that this platform type, as a rule, has a BIOS setting "Command Rate: 1T/2T", while the other modern platforms (for example, Intel Pentium 4 with chipsets Intel 915, 925, 945, 955, and 975) lack settings of command interface delays; they are most likely controlled automatically. Let's get back to AMD Athlon 64. In 2T mode, all commands (together with corresponding addresses) are executed for two memory bus cycles, which definitely affects performance. But it can be justified from the point of view of memory stability. We shall review this issue in detail in future (in the second "practical" part of this guide, devoted to choosing SDRAM modules).
DDR/DDR2 SDRAM: Differences from SDR SDRAM
We have reviewed organization and operation principles of SDR SDRAM devices. This section will review the main differences, brought by DDR and DDR2 SDRAM.
Let's start with DDR SDRAM. These devices are mostly similar to SDR SDRAM chips — as a rule, both types have the same logical organization (in case of the same capacity), including 4-banked organization of the memory array and the same command-address interface. Fundamental differences between SDR and DDR lie in the organization of the logical layer of the data interface. Data are transferred along the data interface of SDR SDRAM memory only on the positive-going edge (rising edge) of the clock signal. The internal frequency of SDRAM chips matches that of the external data bus. Width of the internal SDR SDRAM data bus (from storage cells to IO buffers) matches the width of the external data bus. At the same time, the data interface of DDR (and DDR2) memory transfers data twice per data bus cycle — on the positive-going pulse (rising edge) and on the negative-going pulse (falling edge).
Here emerges the question as to how to organize double transfer rate with respect to the memory bus frequency? Two solutions come to mind — either double the internal operation frequency of memory chips (compared to the frequency of the external bus), or double the width of the internal data bus (compared to the width of the external bus). It would be too naive to think that DDR standard uses the first solution. But it's easy to make this mistake, considering the purely marketing approach to marking DDR memory modules, supposedly operating at the double rate (for example, DDR modules with the real bus frequency of 200 MHz are called DDR-400). Nevertheless, the second solution is much simpler and more efficient in technological and economical terms. So it's used in DDR SDRAM devices. This architecture, used in DDR SDRAM, is called a 2n-prefetch architecture. Data access in this architecture is done "pairwise" — each single READ command sends two elements on the external data bus (their capacity, as in SDR SDRAM, being equal to capacity of the external data bus). In the same way, each WRITE command waits for the arrival of two elements on the external data bus. This very fact explains why Burst Length (BL) cannot be less than 2 for transferring data in DDR SDRAM devices.
DDR2 SDRAM devices are a logical development of the 2n-prefetch architecture, used in DDR SDRAM devices. It's natural to assume that the architecture of DDR2 SDRAM devices is called 4n-prefetch and the internal data bus width is four times (not two times) as large compared to the width of the external data bus. But we are not speaking here of further increase in the number of data elements, transferred per cycle of the external data bus — or such devices wouldn't have been called Double Data Rate devices of the second generation. Instead, further expansion of the internal data bus allows to half the internal operation frequency of DDR2 SDRAM devices compared to the operation frequency of DDR SDRAM chips with the same theoretical bandwidth. On one hand, the reduction of the internal operation frequency of memory chips together with the reduction of the nominal voltage from 2.5 V to 1.8 V (thanks to the new 90-nm process technology) allows a noticeable reduction in memory power consumption. On the other hand, the 4n-prefetch architecture of DDR2 chips allows to reach twice as high frequency of the external data bus compared to the frequency of the external data bus in DDR chips — the internal operation frequency of their chips being equal. That's exactly what we see nowadays — standard DDR2-800 memory modules (400 MHz data bus) are currently rather popular on the memory market, while the last official DDR standard is limited to DDR-400 (200 MHz data bus).
You can get detailed information about DDR2 and its main differences from DDR in our article DDR2 - a future replacement of DDR. Theoretical basics and the first low-level test results. And now, on the analogy of DDR, we can only see how much data are read/written in DDR2 chips and what is the minimal burst length. As DDR2 is just like the old DDR, we still have double transfer rate per cycle of the external data bus — in other words, we expect to get no less than two data elements per cycle of the external data bus (as always, their capacity equals that of the external data bus) for reading and must provide no less than two data elements to the memory chip for writing. At the same time, remember that the internal operation frequency of DDR2 chips is only half of its external interface frequency. Thus, there are two "external" cycles per each "internal" cycle of a memory chip. And each of them in its turn allows to read/write two data elements. Thus, four data elements are read/written per "internal" cycle of a memory chip (hence the title — 4n-prefetch). That is all operations inside a memory chip are carried out on the level of 4-element chunks of data. So the minimal burst length (BL) must be 4. In fact, it can be proved that in the general case the minimal Burst Length (2n) always corresponds to the "2nn-prefetch" architecture (n = 0 corresponds to DDR; n = 1 — DDR2; n = 2 — future DDR3).

Observations:
•	This can't be shown in the recorded results, but from my observations during testing, I noticed the general trend that as memory timings are set more and more aggressively, Sandra would reach it's steady-state score quicker and quicker (A gradual decrease from 5-7 trial runs to achieve a steady-state value to about 2-3 runs). 
•	The overall bandwidth increase from the slowest memory timings to the fastest memory timings (1333 --> 2303) was approximately 73% (970 MB/sec). 
General Trends:
These are just some general trends that I noticed when I was doing an analysis of my data:
Memory Clock Speed:
The speed of memory is most commonly measured by the clock speed, basically the number of cycles per second. Ram running at 133 MHz basically goes through 133 million clock cycles a second.
Clock Speed:	Performance Gain:	% Increase:	Theoretical %:
100 to 133	~500 MB/sec	35-40%	33%
133 to 166	~200-300MB/sec	10-15%	25%
100 to 166	~750-800MB/sec	55-60%	66%
The performance gain from increasing the memory clock speed looks to be subject to the law of diminishing returns, with larger performance gains when moving from lower clock speeds.
CAS:
CAS latency is basically the number of clock cycles (or Ticks, denoted with T) between the receipt of a "read" command and when the ram chip actually starts reading. Obviously, lower numbers will result in less of a delay when memory is being read from. Corsair's website claims a low single digit % gain from CAS-3 to CAS-2. Memory can be basically visualized as a table of cell locations, and the CAS delay is invoked every time the column changes (which is far more often than the row changing)..
CAS Latency:	Performance Gain:	% Increase:
3.0 to 2.5	~0-2MB/sec	0%-0.001%
2.5 to 2.0	~0-3MB/sec	0%-0.002%
2.0 to 1.5	~0-3MB/sec	0%-0.002%
3.0 to 2.0
(166 MHz mem clock)	~0-4MB/sec	0%-0.002%
3.0 to 1.5
(100 MHz mem clock)	~0-4MB/sec	0%-0.002%
The differences in memory bandwidth concerning CAS latency were non-existent (and it is just as likely that any recorded performance gains are attributed to random events, as performance gains were not at all consistent). There was no significant gain in memory bandwidth from adjusting CAS latencies.
Additional Reading/References:
•	Corsair's information page on CAS latency (http://www.corsairmemory.com/main/trg-cas.html) 
•	Adrian's Rojak Pot: Bios Optimization Guide - SDRAM CAS Latency Time (http://www.rojakpot.com/showBOG.aspx?bogno=117) 

Bank Interleave:
In layman's terms, Bank interleaving changes the way "banks" (basically, chunks of memory) are accessed and refreshed. Basically a staggered effect is created to minimize the overall refresh and access delays, sending a read/access command to a certain bank of memory while waiting for the results of a previous read/access command. All memory chips over 64 megs have 4-banks (and can utilize this option).
Bank Interleave:	Performance Gain:	% Increase:
Disabled to 2-Way	40-50MB/sec	1%-4%
2-Way to 4-Way	40-50MB/sec	1%-4%
Disabled to 4-Way	80-100MB/sec	2%-8%
Performance gains concerning bank interleave were very consistent, with a 40-50 point increase across the board, completely independent of all other settings. Of course, at higher speeds this performance gain is less significant (1% at 166 FSB compared to 4% at 100 FSB - meaning that the increase does not scale with faster speeds).
Additional Reading/References:
•	Ars Technica: BIOS Arcana - Description and Translation (http://www.arstechnica.com/guide/building/bios/bios-1.html) 
•	Adrian's Rojak Pot: Bios Optimization Guide - SDRAM Bank Interleave (http://www.rojakpot.com/showBOG.aspx?bogno=116) 

Precharge to Active (tRP):
The Precharge to Active timing controls the length of the delay between the precharge and activation commands. This influences row activation time which is taken into account when memory has hit the last column in a specific row, or when an entirely different memory location is requested.
tRP:	Performance Gain:	% Increase:
3T to 2T	10-20MB/sec	.1%
The gain from optimizing the tRP value seemed to scale with higher FSBs (10MB/sec at 100 FSB, 20MB/sec at 166 FSB), giving a consistent .1% increase in performance. I highly doubt that this .1% in memory bandwidth would translate to a noticeable (or significant) real world increase.
Additional Reading/References:
•	Adrian's Rojak Pot: Bios Optimization Guide - SDRAM Trp Timing Value (http://www.rojakpot.com/showBOG.aspx?bogno=116) 

Active to Precharge (tRAS):
The Active to Precharge timing controls the length of the delay between the activation and precharge commands -- basically how long after activation can the access cycle be started again. This influences row activation time which is taken into account when memory has hit the last column in a specific row, or when an entirely different memory location is requested.
tRAS:	Performance Gain:	% Increase:
7T to 6T	~0-3MB/sec	0%-0.001%
As with CAS, the performance gain was inconsistent, and possibly could be attributed to random variables.
Additional Reading/References:
•	Adrian's Rojak Pot: Bios Optimization Guide - SDRAM Tras Timing Value (http://www.rojakpot.com/default.aspx?location=4&var1=126) 

Active to CMD (Trcd):
This timing controls the length of the delay between when a memory bank is activated to when a read/write command is sent to that bank. This basically comes into play when the memory locations are not accessed in a linear fashion (because in a linear fashion, the current bank is already activated).
tRCD:	Performance Gain:	% Increase:
3T to 2T	20-30MB/sec	1.0%-1.5%
This option gave a consistent 20-30 MB/sec gain in memory bandwidth, with the results slightly pointing to a slight scaling at lower CAS latencies and higher FSBs.
Additional Reading/References:
•	Adrian's Rojak Pot: Bios Optimization Guide - SDRAM Trcd Timing Value (http://www.rojakpot.com/default.aspx?location=4&var1=127) 
•	Lost Circuits: High Performance DDR DIMMs (http://www.lostcircuits.com/memory/ddr2/3.shtml) 

DRAM Command Rate (self-abbreviated DRC):
I'm going to take a quote from Adrian's Rojak Pot in order to explain this setting:
This BIOS feature controls how long the memory controller latches on and asserts the command bus. The lower the value, the faster the the memory controller can send commands out.
DRC:	Performance Gain:	% Increase:
2T to 1T	~30MB/sec	1.1%-2.1%
A faster DRAM Command Rate results in a consistent 30MB/sec gain in memory bandwidth.
Additional Reading/References:
•	Adrian's Rojak Pot: Bios Optimization Guide - SDRAM Command Rate (http://www.rojakpot.com/default.aspx?location=4&var1=196) 
•	Lost Circuits: High Performance DDR DIMMs (http://www.lostcircuits.com/memory/ddr2/4.shtml) 

DRAM Burst Length (self-abbreviated DBL):
This option basically controls the amount of data that can be "burst" in one read/write. A "burst" has the advantages of only needing to invoke the CAS latency one time, allowing for less delay than a "non-burst" transaction. However, "burst" transactions can only be used for contiguous blocks of data (as only one column address is sent in the burst).
DBL:	Performance Gain:	% Increase:
4 to 8	0 MB/sec	0%
Our results showed no performance increase at all with changing the DRAM Burst Length, no matter what the circumstances were.
Additional Reading/References:
•	Adrian's Rojak Pot: Bios Optimization Guide - SDRAM Burst Length (http://www.rojakpot.com/default.aspx?location=4&var1=195) 

Write Recovery Time (tWR):
The Write Recovery Time memory timing determines the delay between a write command and a precharge command is set to the same bank of memory. According to Adrian's Rojak Pot, this option improves memory performance as well as provides increased overclockability.
tWR:	Performance Gain:	% Increase:
3T to 2T	0%	0%
Our results showed no performance increase at all with changing the the Write Recovery Time. This option had no influence on the overclockability of our test RAM (i.e. the test bed still crashed at more aggressive memory timings).
Additional Reading/References:
•	Adrian's Rojak Pot: Bios Optimization Guide - SDRAM Burst Length (http://www.rojakpot.com/default.aspx?location=4&var1=157) 

DRAM Access Time (self-abbreviated DAT):
I personally have no idea what this BIOS setting does (and the motherboard manual gives no clues either). My references also have no information on this setting.
DAT:	Performance Gain:	% Increase:
3T to 2T	0-3MB/sec	0%-0.002%
From our results, the most important factor in memory bandwidth is the speed of the memory clock. This would suggest a certain desirability to sacrifice the other memory timings in hopes of pushing the memory speed higher. However, as our results revealed, the speed of the memory combined with CAS latency has the most affect on the overclockability of a memory stick (our test memory would not run at the more aggressive speeds and CAS latencies). The memory timings on our particular setup that had the most impact on performance involved setting the Bank Interleave to 4 Way, decreasing the DRAM command rate to 1T, and decreasing tRCD to 1T. Just as other websites have suggested gains from certain memory timings (the Engineers at OCZ suggest that tRAS at 3T or 4T have a very significant increase on performance), I should remind you that these are my personal results from my test setup, and my particular combination of hardware created these "patterns."

Mysterious Bios Settings



Memory timings 

Memory performance is not entirely determined by bandwidth, but also the speeds at which it responds to a command or the times it must wait before it can start or finish the processes of reading or writing data. These are memory latencies or reaction times (timings). Memory timings control the way your memory is accessed and can be either a contributing factor to better or worse 'real-world' performance of your system. 

Internally DRAM has a huge array of cells that contain data. (If you've ever used Microsoft's Excel, try and picture it that way) A pair of row and column addresses can uniquely address each cell in the DRAM. DRAM communicates with a memory controller through two main groups of signals: Control-Address signals and Data signals. These signals are sent to the RAM in order for it to read/write data, address and control. The address is of course where the data is located on the memory banks, and the control signals are various commands needed to read or write. There are delays before a control signal can be executed or finish and this is where we get memory timings. The standard format for memory timings are most often expressed as a string of four numbers, separated by dashes, from left to right or vice-versa like this 2-2-2-5 [CAS-tRP-tRCD-tRAS] . These values represent how many clock cycles long each delay is but are not expressed in the order in which they occur. Different bioses will display them differently and there maybe additional options (timings) available.




Which timings mean what?

In most motherboards, numerous settings can be found to optimize your memory. These settings are often found the Advanced Chipset section of the popular award bioses. In certain instances, the settings maybe placed in odd locations, so please consult your motherboard manual for specific information. Below are common latency options:
•	Command rate - is the delay (in clock cycles) between when chip select is asserted (i.e. the RAM is selected) and commands (i.e. Activate Row) can be issued to the RAM. Typical values are 1T (one clock cycle) and 2T (two clock cycles). 
•	CAS (Column Address Strobe or Column Address Select) - is the number of clock cycles (or Ticks, denoted with T) between the issuance of the READ command and when the data arrives at the data bus. Memory can be visualized as a table of cell locations and the CAS delay is invoked every time the column changes, which is more often than row changing. 
•	tRP (RAS Precharge Delay) - is the speed or length of time that it takes DRAM to terminate one row access and start another. In simpler terms, it means switching memory banks. 
•	tRCD (RAS (Row Access Strobe) to CAS delay) - As it says it's the time between RAS and CAS access, ie. the delay between when a memory bank is activated to when a read/write command is sent to that bank. Picture an Excel spreadsheet with a number across the top and along the left side. They numbers down the left side represent the Rows and the numbers across the top represent the Columns. The time it would take you, for example, to move down to Row 20 and across to Column 20 is RAS to CAS. 
•	tRAS (Active to Precharge or Active Precharge Delay) - controls the length of the delay between the activation and precharge commands ---- basically how long after activation can the access cycle be started again. This influences row activation time which is taken into account when memory has hit the last column in a specific row, or when an entirely different memory location is requested.


These timings or delays occur in a particular order. When a Row of memory is activated to be read by the memory controller, there is a delay before the data on that Row is ready to be accessed, this is known as tRCD (RAS to CAS, or Row Address Strobe to Column Access Strobe delay). Once the contents of the row have been activated, a read command is sent, again by the memory controller, and the delay before it starts actually reading is the CAS (Column Access Strobe) latency. When reading is complete, the Row of data must be de-activated, which requires another delay, known as tRP (RAS Precharge), before another Row can be activated. The final value is tRAS, which occurs whenever the controller has to address different rows in a RAM chip. Once a row is activated, it cannot be de-activated until the delay of tRAS is over. 


To tweak or not to tweak?

In order to really maximize performance from your memory, you'll need to gain access to your system's bios. There is usually a Master Memory setting, often rightly called Memory Timing or Interface, which gives usually gives you the choice to set your memory timings by SPD or Auto, preset Optimal and Aggressive timings (e.g. turbo and ultra), and lastly an Expert or Manual setting that will enable you to manipulate individual memory timing settings to your liking.

Are the gains of the perfect, hand-tweaked memory timing settings worth it over the automatic settings? If you're just looking to run at stock speeds and want absolute stability, then the answer to that question would probably be no. The relevance would be nominal at best and you would be better off going by SPD or Auto. However, if your setup is up on the cutting edge of technology or you’re pushing performance to the limit as do some overclockers, or gamers or tweakers, it may have great relevance.

SPD (Serial Presence Detect)

SPD is a feature available on all DDR modules. This feature solves compatibility problems by making it easier for the BIOS to properly configure the system to optimize your memory. The SPD device is an EEPROM (Electrically Erasable Programmable Read Only Memory) chip, located on the memory module itself that stores information about the DIMM modules' size, timings, speed, data width, voltage, and other parameters. If you configure your memory by SPD, the bios will read those parameters during the POST routine (bootup) and will automatically adjust values in the BIOS according preset module manufacturer specifications.

There is one caveat though. At times the SPD contents are not read correctly by the bios. With certain combinations of motherboard, bios, and memory setting SPD or Auto may result in the bios selecting full-fast timings (lowest possible numbers), or at times full-slow timings (highest possible numbers). This is often the culprit in situations where it appears that a particular memory module is not compatible with a given board. Often in these cases the SPD contents are not being read correctly and the bios is using faster memory timings than the module or system as a whole can boot with. In cases like these try replacing the module with another, setting the bios to allow manual timings, and setting those timings to safer (higher) values will allow the combination to work.


Ok so I want to tweak, what do I do?

Now for the kewl stuff!!!

The first order of business, when tweaking your memory, is to deactivate the automatic RAM configuration -- SPD or Auto. With SPD enabled, the SPD chip on the memory module is read to obtain information about the timings, voltage and clock speed and those settings are adjusted accordingly. These settings are, however, very conservative to ensure stable operation on as many systems as possible. With a manual configuration, you can customize these settings for your own system and in most cases, the memory modules will remain stable even when they exceed the manufacturer's specifications.

As a general rule, a lower number (or timing) will result in improved performance. After all, if it takes fewer cycles to complete an operation, then it can fit more operations within X amount of time. However, this comes at a cost, and that is stability. It is similar to wireless networking with short and long preambles. A long pre-amble might be slower, but in a heavy network environment it is much more reliable than short preamble because there is more certainty a packet is for your NIC. The same is for memory - the more cycles used, in general, the more stable the performance. This is inherently true for all of them because to access precisely the right part of the memory, you have to be accurate, and the more time to do a calculation will make it more accurate in this instance. Most typical values are 2 and 3. You might ask: Why can't we use 1 or even 0 values for memory timings? JEDEC specifies that it's not possible for current DRAM technology to operate as it should under such conditions. Depending on motherboard, you might be able to squeeze '1' on certain timings, but will very likely result memory errors and instability. And even if it doesn't, it is unlikely to result in a performance gain.

If you are not planning on overclocking the clock speed of your RAM or if you have fast RAM rated at speeds above that of your current FSB, it may be possible to just lower the timings for a performance gain in certain applications that require most frequent accesses to system memory like, for instance, games. Memory timings can vary depending on the performance of RAM chips used. Not all memory modules will exhibit the ability to use certain timings without producing errors. So testing, trial and error, is required.

Here are general guidelines to follow while "tweaking":
•	As with CPU/video card overclocking, adjusting the memory timings should be done methodically and with ample time to test each adjustment. 
•	lower figures = better performance, but lower overclockability and possibly diminished stability. 
•	higher figures = lesser performance, but increased overclockability and more stability -- to an extent 
•	tRCD & tRP are usually equal numbers between 2 and 4. In tweaking for more overclockability, lower tRP first between these two 
•	CAS should be either 2.0 or 2.5. Many systems, most nforce2, fail to boot with a 3.0 setting or have stability problems. CAS is not most critical of the various timings, unlike what is taught by many. In general, the importance of CAS when placed against tRP and tRCD is nominal. Reducing CAS has a relatively minor effect on memory performance, while lower tRP & tRCD values result in a much more substantial gain. In other words if you had to choose, 3-3-2.5 would be better than 4-4-2.0 (tRCD-tRP-CAS) 
•	tRAS should always be larger the before mentioned timings. – see below


tRAS is unique, in that lowering it can lead to problems and lesser performance. tRAS is the only timing that has no effect on real performance, if it is configured as it should. By definition, real-life performance is the same with different tRAS settings with a certain exception. This document from Mushkin outlines how tRAS should be a sum of tRCD, CAS, and 2. For example, if you are using a tRCD of 2 and a CAS of 2 on your RAM, then you should set tRAS to 6. At values lower than that theory would dictate lesser performance as well as catastrophic consequences for data integrity including hard drive addressing schemes --- truncation, data corruption, etc --- as a cycle or process would be ended before it's done. How is it possible for memory timings to affect my hard drive? When the system is shut down or a program is closed, physical ram data that becomes corrupted may be written back to the hard drive and that’s where the consequences for the hard drive come in. Also let’s not forget when physical ram data is translated by the operating system to virtual memory space located on the hard drive.

While it's important to consider the advice of experts like Mushkin, your own testing is still valuable. Systems – both AMD & Intel alike, can indeed operate with stability with 2-2-2-5 timings, and even exhibit a performance gain as compared to the theoretically mandated 2-2-2-6 configuration. The most important thing in any endeavor is to keep an open mind, and don't spare the effort. Once you've tried both approaches extensively it will be clear to you which is superior for your particular combination of components.


The Anomaly: nVIDIA’s nForce2 and tRAS

An anomaly can be described as something that’s difficult to classify; a deviation from the norm or common form. This is exactly the situation with tRAS (Active to Precharge) and nVIDIA’s nforce2 chipset. As said before, not sparing the effort is what has lead to the initial discovery of this anomaly many months ago. It’s pretty well known by now, in a nutshell, a higher tRAS (i.e. higher than, say, the Mushkin mandated sum of CAS+tRCD+2) on nforce2 motherboards consistently shows slightly better results in several benchmarks and programs. In most cases, 11 seems to be the magic number. Other chipsets do not display this “deviation from the norm”, so what makes the nforce2 different?

This thread has been on the topic for a while now, and TheOtherDude has given a possible explanation for this anomaly.

“Unlike most modern chipsets, the Nforce2 doesn't seem to make internal adjustments when you change the tRAS setting in the BIOS. These "internal" (not really sure if that’s the right word) settings seem to include Bank Interleave, Burst Rate and maybe even Auto-precharge. For optimal performance, tRAS (as measured in clock cycles) should equal the sum of burst length, plus the finite time it takes the RAM to conduct a number of clock independent operations involved with closing a bank (~40 ns) minus one clock if Auto-precharge is enabled (this factor can be slightly effected by CAS, but should not play a role in optimal tRAS). To complicate things even more, one bank cannot precharge a row while the other specifies a column. This brings tRCD into the mix.

Higher isn't always better, but the reason everything is so weird with tRAS and the Nforce2 is simply because the chipset doesn't make the internal optimizations to accommodate your inputted tRAS value like most other chipsets.”




Dealing with Memory Speeds / Frequencies

When the memory frequency runs at the same speed as the FSB, it is said to be running in synchronous operation. When memory and FSB are clocked differently (lower or higher than), it is known to be in asynchronous mode. On both AMD and Intel platforms, the most performance benefits are seen when the FSB of the processor is run synchronously with the memory – Although Intel based systems have a slight exception, this is completely true of all AMD-supporting chipsets. When looking at the AMD-supporting chipsets async modes are to be avoided like a plague. AMD-supporting chipsets offer less flexibility in this regard due to poorly implemented async modes. Even if it means running our memory clock speed well below the maximum feasible for a given memory, an Athlon XP system will ALWAYS exhibit best performance running the memory in sync with the FSB. Therefore, a 166FSB Athlon XP would run synchronously with DDR333/PC2700 (2*166) and give better performance than running with DDR400/PC3200, despite its numbers being bigger. 

Only Intel chipsets have implemented async modes that have any merit. If you are talking about the older i845 series of chipsets, running an async mode that runs the memory faster than the FSB is crucial to top system performance. And with the newer dual channel Intel chipset (i865/875 series) in an overclocked configuration, often you must run an async mode that runs the memory slower than the FSB for optimal results. The async modes in SiS P4 chipsets also work correctly.
To achieve synchronous operation, there is usually a Memory Frequency or DRAM ratio setting in the bios of your system that will allow you to manipulate the memory speed to a either a percentage of the FSB (i.e. 100%) or a fraction (or ratio) i.e. N/N where N is any integer available to you. If you want to run memory at non 1:1 ratio speeds, motherboards use dividers that create a ratio of CPU FSB: memory frequency. However, intrinsically, it is possible to see the problem with this and why synchronous operation is preferable on all PC platforms. If there is divider, then there is going to be a gap between the time that data is available for the memory, and when the memory is available to accept the data (or vica versa). There will also be a mismatch between the amount of data the CPU can send to the memory and how much the memory can accept from the CPU. This will cause slowdowns as you will be limited by the slowest component. 
Here are three examples illustrating the three possible states of memory operation:
200MHz FSB speed with 100% or 1:1 (FSB:Memory ratio) results in 200MHz memory speed (DDR400)

Such a configuration is wholly acceptable for any AMD system, memory should be set this way at all times for best performance. Asynchronous FSB/Memory Speeds are horridly inefficient on AMD systems, but may well be the optimal configuration for P4 systems.
200MHz FSB speed with 120% or 5:6 (FSB:Memory ratio) results in 240MHz memory speed (DDR480)

This example shows running the memory at higher asynchronous speeds. Assume we have a Barton 2500+ which by default is running at a FSB of 333 MHz (166 MHz X 2) and we also have PC3200 memory which by default is running at 400 MHz. This is a typical scenario because many people think that faster memory running at 400 MHz, will speed up their system. Or they fail to disable the SPD or Auto setting in their bios. There is NO benefit at all derived from running your memory at a higher frequency (MHz) than your FSB on Athlon XP/Duron sytems. In actuality, doing so has a negative effect.

Why does this happen? It happens because the memory and FSB can't "talk" at the same speeds, even though the memory is running at higher speeds than the FSB. The memory would have to "wait for the FSB to catch up", because higher async speeds forces de-synchronization of the memory and FSB frequencies and therefore increases the initial access latency on the memory path -- causing as much as a 5% degradation in performance.

This is another ramification of the limiting effect of the AMD dual-pumped FSB. A P4's quad pumped FSB (along with the superior optimization of the async modes) allows P4's to benefit in some cases from async modes that run the memory faster than the FSB. This is especially true of single channel P4 systems. There still are synchronization losses inherent in an async mode on any system, but the adequate FSB bandwidth of the P4 allows the additional memory bandwidth produced by async operation to overcome these losses and produce a net gain.
__________________

The impact of latency 
Why are latencies important? In short, latency means the time from when an access is issued until the critical data are available. Latencies are a universal phenomenon and a main determining performance factor for the CPU cache, the HDD (access time), the PCI bus and any other component of any computer system, including the main memory. This article focuses only on the latter factor, that is the system memory. For a detailed introduction of how memory works, the PC-guide has the most comprehensive information. A more compressed version of the different timing issues relating to performance is found in our own articles on ESDRAM, HSDRAM and Corsair PC 133 DIMMs. For those interested in more architectural questions, a good write-up has been posted on Aces Hardware. 
Briefly, the current chipsets allow to vary three timing parameters: 
CAS Delay (CAS): 2-3 cycles 
RAS-to-CAS Delay (tRCD): 2-3 cycles 
RAS Precharge (tRP): 2-3 cycles 
From these numbers, it is possible to calculate that, at 3:3:3 settings, a total of 10 bus cycles is necessary to release four words (Bytes). At 2:2:2 settings. the same would be accomplished within 8 cycles (precharge latency is not as important since the precharge can already start while the third word is output). Increasing either CAS Delay or tRCD to 3 cycles will result in 9 bus cycles / 4 bytes, however, this simple equation only holds for totally random accesses. In real life applications, CAS delay is much more important than RAS-to-CAS delay as we'll see in the next paragraph. 
A simplified, three paragraph explanation of memory latencies 
Data are written to and read from memory in a relatively ordered manner, that is, most of the time coherent data are stored within the same row (high locality) where only the column address changes, meaning activation of the Column Address Strobe only. From a performance standpoint, therefore, the most important of the three timing parameters is the CAS delay. Since this is important, I'll rephrase it one more time: most of the time, data that belong together are stored in contiguous blocks within the same row. In turn, this means that for consecutive single word or burst reads, only the new column address needs to be specified which which is then accessed by the column address strobe (CAS). If the data are not found within the same row, they have to be retrieved elsewhere and that involves delays from the bank activate command to the read command (RAS-to-CAS delay) and the CAS delay. 
What about the precharge? Data are electrical charges that are coming out of the memory cell (1 capacitor) and after a copy of these data has been generated in the sense amplifiers, the original has to be moved back to the cell of origin and stored (precharge). The tRP latency is of minor importance since the precharge can start as soon as the 3rd word of a burst write is being output and, thus the latency is masked. 
The specs of the various chipsets , e.g., the page hit limitation (PH limit) in the AMD 751 North Bridge allow to predict how many times data can be retrieved from within the same row, and even though the individual application plays an important role, we can estimate that a mandatory tRCD occurs only every 32to 64 reads (depending on the BIOS settings). Under normal circumstances, the counter treats any transaction alike, that is, it does not differentiate between single word and burst reads. Therefore, the CAS delay occurs as much 64 times as often as the RAS-to-CAS delay (This only holds for optimal conditions, in real life, the ratio would most likely be in the order of 10:1 or 20:1). More details details would fill a book but who would read it anyway? 
BASICS - RAM TIMINGS/LATENCIES - WHAT THE HELL ARE THOSE??
Ok, for those who do not know anything about this, RAM timings are the 2-2-2-5 and the 2-3-3-7 and the 3-4-4-8 that the veterans always talk about when it comes to RAM. Now what are these numbers really? To put things really simply, they actually refer to the delay timings of a certain stick of RAM. And as you might have figured out, less delays mean faster RAM. So, to put it simply and accurately, the lower or tighter the timings/delays, the faster the RAM is. Meaning 2-2-2-5 is faster than 3-4-4-8. Yup, told you it was simple. Please keep in mind that all the above was assuming that the clockspeed of the RAM remains the same, only timings different. 
Not all RAM can run at the tightest/best timing of 2-2-2-5. Generally, high-quality lower speed RAM like DDR400 will have tighter timings, while most DDR500 RAM have loose/relaxed timings (usually 3-4-4-8).

Now, I will explain briefly the most common RAM timings for a P4 mainboard, and how they affect performance.

Refer to the picture above for what I will talk about here.
Now, get into the Advanced Chipset Features menu in the BIOS (or something similar to that, not all BIOS are the same) You will see a row of numbers like 3, 8, 4, 4 or 3, 4, 4, 8 or whatever other arrangement they might have, depending on the BIOS. These are the most important settings for your RAM. Now I will explain in minimal detail what the settings are.
DRAM Timing Selectable (Options - Manual, By SPD)
This refers to the settings of the 3 timings I will explain below. By SPD means that the timings are set by the BIOS automatically to the default suggested by the manufacturer. The timings in By SPD mode can be used as a reference/default. Since you want to tweak the settings, set this to Manual.
CAS Latency Time (Options - 2, 2.5, 3)
This refers to the Column Address Strobe delay time. Lower is better! However, in a P4 system, lowering this setting only improves performance minimally, so it might be better to increase this setting to gain stability or a higher overclock.
Act to Precharge Delay (Options - 5, 6, 7, 8)
This refers to the Active to Precharge delay time. Lower is better! However, same as above, lowering this setting only improves performance minimally, so it might be better to increase this setting to gain stability or a higher overclock.
DRAM RAS# to CAS# Delay (Options - 2, 3, 4)
This refers to the Row Address Strobe to Column Address Strobe delay time. Lower is better! This is the most crucial setting in a P4 system! Lowering this setting improves performance quite noticeably, so you might want to sacrifice some clockspeed to lower this timing.
DRAM RAS# Precharge (Options - 2, 3, 4)
This refers to the Row Address Strobe to Column Address Strobe delay time. Lower is better! This is the 2nd most crucial setting in a P4 system! Lowering this setting improves performance quite noticeably, so you might want to sacrifice some clockspeed to lower this timing.
Leave all those other settings at their defaults.
THINGS TO REMEMBER
1.	When someone refers to RAM timings as 2-3-4-5, they usually mean, from 1st number to the last number: 
a.	2- CAS latency time 
b.	3- RAS# to CAS# delay 
c.	4- RAS# Precharge 
d.	5- Act to Precharge Delay

2.	Keep in mind that if you lower the RAM timings too much, your system be unstable or might not boot. If this happens, turn off your computer and wait at least 30 seconds. Just press and hold the INSERT key when turning on your PC again and all should be fine.

3.	Different RAM sticks are made for different things. 
a.	Some RAM sticks are built for lower clockspeeds and tight timings. For example, DDR 400 with 2-2-2-5 timings. However, RAM like this can seldom reach high clockspeeds. 
b.	Some are built for super-high clockspeeds and more relaxed/higher latencies. For example DDR500 with 3-4-4-8 timings. These RAM usually cannot run at super tight timings, but can achieve speeds of 250MHz or more. 
c.	There is always a compromise between clockspeeds and latency. Lower latencies usually mean lower clockspeeds. Higher clockspeeds mean higher latencies. 
4.	Timings and clockspeeds affect the performance of the RAM. So, the perfect RAM will be able to run at super high clockspeeds (DDR500+), and at super low latencies (2-2-2-5). However, there is no RAM that can do this at the moment.

Remember that a good RAM overclock does not mean the highest clockspeeds or tightest timings, but rather a good balance between the two. I cannot possibly tell each and every one of you the optimal settings for your system, as there are too many combinations. So you will have to spend some time experimenting to see which settings gives you the best combination. 
I personally think that the best RAM to get for the P4 is ultra low latency DDR400/DDR433 RAM that can run at 2-3-2-6 or lower. This RAM is the most flexible to overclock with and the performance comes close to most DDR500 RAM because of the tighter timings. 
Or, better still, get memory that can operate at low clockspeeds with low latencies, and higher clockspeeds with higher latencies. This way, you can tweak the settings to your heart's content! My personal favorite is OCZ PC3700 Gold Rev. 2. Read a review about this awesome memory here. 
However, the best RAM may not be the easiest to tweak. The easiest RAM to overclock with is high quality DDR500 or DDR533 RAM. With this RAM, you do not have to mess around with many settings. More details on the next page.

ASUS BOARDS
Click on thumbnail to view full picture
For ASUS board users, Set the AI Overclock Tuner to [Manual]. The option to adjust the RAM ratio is the DRAM Frequency option. Here are the settings:
1.	Auto - Sets the divider to the default ratio This usually means a ratio of 1:1.

2.	DDR400 (which means 1:1)- This means that the RAM will run at the same speed as the FSB

3.	DDR333 (which means 5:4) - This means that the RAM will run at FSB*(4/5) or in other words FSB*(0.8)

4.	DDR266 (which means 3:2) - This means that the RAM will run at FSB*(2/3) or in other words FSB*(0.667) 
General guidelines for DDR500+:
Ok, simply said what you are gunning for is the highest 1:1 ratio when you overclock. Working with this RAM is the easiest:
1.	Increase the DDR SDRAM Voltage to 2.8v (or 3.0v if your mainboard can do it).

2.	Change the RAM timings to the highest latencies (3-4-4-8)

3.	Set the DRAM Ratio to 1:1.

4.	You should be able to reach 250MHz FSB speed with no problems. Some good quality DDR500 RAM can go up to 270MHz easily.

5.	Once you are done with the overclock, Prime95 with the settings on this page to test the stability. If it runs stable for at least an hour, then you are done (this is assuming that your CPU is stable at those FSB settings). If there are errors, you will have to reduce the speed a little bit and test again.

6.	After you find a stable setting, you may even want to tighten some timings a little bit to improve performance further. Just keep in mind that this type of RAM can hardly run at tighter timings. Experiment and run stability tests, play all your favorite games, benchmarks etc.

7.	Remember that some DDR500+ RAM may not work at any divider other than 1:1 on some mainboards. Well, it seldom matters anyway because 1:1 is what you want with this RAM. 
As you noticed, for DDR500, it is better to sacrifice some latency for more MHz.

General guidelines for DDR400 built for tight timings (2-3-3-7 or below):
Now, this type of RAM is a bit tricky to work with because it involves dividers, and a some mainboards are really picky when it comes to certain RAM brands and may not work properly with some dividers. However, this RAM is usually cheap and readily available. Here are the general guidelines for working with DDR400 RAM built for tight timings:
1.	Increase the DDR SDRAM Voltage to 2.8v. You can increase it more if you like, but most DDR 400

2.	You may want to test out the lowest timings/latencies it can do at default clockspeeds (200MHz). Lower the timings one by one and test out all the possible combinations to see which combination is stable. Run Prime95 torture test for at least half an hour for each setting you try out. Yes, you will have to spend a LOT of time on this one.

3.	Once you have determined the lowest latencies your RAM can do at default clockspeeds, increase the FSB slowly and test the speeds at which it can operate at the tightest timings.

4.	If your CPU can reach 250MHz FSB stable, then it is best to use the 5:4 DRAM Ratio. This means that the RAM is running at 200MHz.

5.	If your CPU can reach 260 - 280MHz FSB stable, you might want to keep the DRAM Ratio at 5:4 and increase the latencies a bit to give more stability and best performance.

6.	If your CPU can reach 280+ FSB, you might want to set the DRAM Ratio to 3:2 and keep the timings as tight as possible.

7.	Prime Prime Prime, never forget to run Prime95 after changing any settings! 

For DDR400/433 built for tight timings, the objective is to keep the timings as low as possible, (as close to 2-2-2-6 as you possibly can). This usually means keeping the RAM speed within the 200-220MHz region.

Prime95 Torture Test Settings - added Jan 30, 2004
1.	Run only 1 instance of Prime95. This is different from testing your CPU where you should run 2 instances. It does not matter which logical CPU it is run on. 
2.	Run the torture test at the Blend setting. This mode will stress your RAM the most. 
3.	Right click the taskbar and open the Task Manager. Your Page File Usage should show a large number (for me it is 600+MB). Your CPU usage should show around 50% after it stabilizes. More than 50% is ok, but from my experience, it should not be constantly below 40%. 

Some DDR400+ are very flexible, so you can follow either the DDR500+ guidelines or the DDR400 guidelines, whichever gives you better performance.
Remember that I cannot possibly go through all the possible combinations of RAM speeds and latency settings. The above are only suggestions/guidelines to give a basic idea. They are not rules that you MUST follow. Every stick of RAM is unique. The rest is up to you to experiment and find the best settings for yourself. You will have to spend a lot of time if you want to tweak it up properly. And please get yourself a good sticks of RAM. Working with cheapy RAM can be a real pain, performance wise and compatibility wise.
Look for the best compromise. Sometimes, increasing the latency by a little bit can allow you to increase the clockspeeds by a lot. This MHz increase may more than make up for the slight performance decrease introduced by increasing the latency. And sometimes, decreasing the clockspeeds a little bit can allow you to tighten the timings by a lot. The tighter timings might give you a bigger performance boost than the extra few MHz. Use benchmarks and games to see which gives you the best performance.
And I cannot say this enough: EXPERIMENT! EXPERIMENT! EXPERIMENT!
This is the only way those hardcore overclockers learn their trade. If you want to become like them, you will have to do what they do.


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## George Safford (Sep 1, 2003)

If the Admins would like to edit this; please feel free...


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## ian_heath (Jan 14, 2007)

Ok. Fellas , this thread is nothing short of astounding - really , the detail covered is just incredible
However ... I did my best to read through all of it but think i will put something out there

I am hoping someone can put me on the right track to getting hold of some "suggested" "öptimum" BIOS settings for overclocking my system.
Here are the core components of my setup

INTEL CORE 2 DUO E6400 CPU (2.13g standard)
HIS X1950 CROSSFIRE EDITION 512mb DDR4 ATI 3D CARD
2 X WD SATA II 160gb hdd (7200/8mb) [Jmicron RAID0 array) 
WD 250gb IDE HDD (7200)
ASUS P5B DELUXE WIFI/AP (Intel P965 / 1066 FSB) [BIOS version 1004]
WINDOWS XP PRO SP2 (OEM)
LG GSA4163B 16x DVD WRITER
ASUS 18x SATA DVD WRITER (WITH LIGHTSCRIBE)
THERMALTAKE TOUGHPOWER 750w PSU (CABLE MANAGEMENT)
2 X (KINGSTON HYPER-X DDR2 PC8500 2x512mb DUAL CHANNEL KIT: KHX8500D2K2/1G) [ie. 2048mb total]

Now I have tried fiddling with the settings and have had some luck but i feel it is the memory settings (Latency etc) that is causing me issues (ie. will not boot at all)

Can someone take a look at the spec sheet found at http://www.kingstonmemory.net.au/downloads/valueram/KHX8500D2K2-1G.pdf

and shed some light on the recommended BIOS settings in the CHIPSET options. The RAM is 2 x Dual Channel and is currently running 2 x Dual channel interlaced fine (4 x matched units)

Cheers
Ian


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## George Safford (Sep 1, 2003)

ian_heath said:


> Ok. Fellas , this thread is nothing short of astounding - really , the detail covered is just incredible
> However ... I did my best to read through all of it but think i will put something out there
> 
> I am hoping someone can put me on the right track to getting hold of some "suggested" "öptimum" BIOS settings for overclocking my system.
> ...


Please go to my other thread where they told me how to overclock my system.

www.techsupportforum.com/hardware-support/motherboards-bios-cpu/121080-pcmark05-system-suite.html


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