# master slave flip flop



## kannushree (Jun 4, 2006)

how are these flip flpos constructed ? where sre they used ? it is said ,dey are internally constructed ,but how ? their use ?


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## UncleMacro (Jan 26, 2005)

A master slave flip flop is made of two flip flops in series with one of them using an inverted clock. This page has a diagram of one at the bottom of the page. They are pulse triggered rather than edge triggered and you have to keep the inputs unchanged while the pulse is high (assuming it's positive pulse). The fact that you have to hold the inputs unchanged while the pulse is high is the main reason you don't often use them.

Whether they're used depends on what kind of clock you have. Most systems use a synchronous system clock with lots of flip flops clocked on one clock edge so the edge triggered flip flops are more commonly used then something like a pulse triggered master slave. In a synchronous system you have a system clock with lots of flip flops clocking on a single system clock edge. They all clock on the edge simulataneously and then their outputs change and ripple through the logic to set up the inputs for the next system clock edge. And that happens over and over as the system moves from one state to the next.

But sometimes chips may have more complicated clocks than a simple synchronous clock so they use different kinds of latches or flip flops. Sometimes they use multiple phased clocks to reduce the number of transistors to get the job done. It just depends on what you're designing. If I'm designing something I just use edge triggered with a synchronous system clock unless I've got a good reason to do something else.


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